“Nvidia Is Hamstrung Too”: Packaging Emerges as AI Chips’ New Bottleneck, Intensifying Global Capex Race

Surging AI accelerator demand pushes TSMC’s CoWoS capacity to its limit
Nvidia may allocate some next-generation GPU production to Intel’s EMIB
SK hynix and Samsung Electronics expand wafer and back-end capacity in tandem

The bottleneck in the artificial intelligence (AI) semiconductor race is spreading from advanced process technology to advanced packaging. As TSMC’s limited packaging capacity prompts Nvidia to consider diversifying its supply chain, South Korean memory chipmakers are expanding wafer production alongside stacking, packaging and testing capabilities to meet growing demand for high-bandwidth memory (HBM). With the competitive arena broadening to encompass substrates, bonding, encapsulants, thermal-management materials and testing equipment, the global investment race in advanced packaging is intensifying.

Nvidia Supply-Chain Pressure Mounts as CoWoS Capacity Runs Short

According to semiconductor research firm SemiAnalysis on July 14 local time, Nvidia is considering allocating a portion of its next-generation graphics processing unit (GPU) production—believed to be codenamed “Feynman”—to Intel’s EMIB process. Although TSMC operates packaging facilities at five locations, including Hsinchu and Tainan in Taiwan, and is pursuing further capacity expansions, it has been unable to keep pace with surging demand for high-performance computing.

At the center of the bottleneck is CoWoS, TSMC’s 2.5-dimensional packaging technology. CoWoS places a GPU or application-specific integrated circuit (ASIC) alongside multiple HBM stacks on an interposer carrying fine-pitch wiring before combining them with a package substrate. The technology shortens the distance between chips, increasing data-transfer bandwidth and power efficiency. As package sizes expand, however, controlling warpage, mechanical stress, heat and fine-pitch bonding defects becomes increasingly difficult. The problem is that packaging capacity has failed to keep pace with demand growth. CoWoS capacity was estimated at approximately 50,000 to 60,000 wafers per month last year. With major customers already securing substantial volumes, however, effective available capacity remains insufficient.

Nvidia previously encountered manufacturing difficulties involving the interposer connecting two compute dies during the initial mass-production ramp of its Blackwell chips in 2024. The Financial Times reported at the time that packaging problems during volume production had weighed on the shipment schedule. The episode demonstrated that even logic dies successfully fabricated on advanced process nodes cannot be converted into finished-product revenue unless sufficient yields are secured when integrating the interposer, HBM and substrate.

Recent reports of delays to Nvidia’s next-generation rack architecture, Kyber NVL144, have further underscored the severity of the packaging bottleneck. According to SemiAnalysis, Kyber NVL144 is likely to be delayed by more than 12 months, potentially pushing its launch into 2028. Manufacturing difficulties involving the PCB midplane that connects modules inside the server rack have been identified as a cause of the delay. Although the component is an internal rack interconnect board distinct from CoWoS, the fundamental challenge lies in translating Nvidia’s ultra-dense AI server design into a manufacturable system. Producing high-performance GPUs and connecting 144 GPUs through an ultra-high-speed network to stabilize them as a single rack-scale system are challenges of an entirely different order. Advanced packaging, HBM integration, high-layer-count PCBs, optical communications, power delivery, liquid cooling, assembly and manufacturing yields must all come together simultaneously.

As TSMC’s internal packaging capacity approaches its limit, some processes are also being distributed to outsourced semiconductor assembly and test (OSAT) providers. Taiwanese companies including ASE and SPIL have begun taking on TSMC’s overflow orders. Taiwanese OSAT providers nevertheless face technological constraints in the most demanding stacking processes, making them unable to serve as complete substitutes. Intel’s EMIB likewise functions as a supplementary option for certain product families rather than a direct replacement for CoWoS. CoWoS places chips and HBM stacks on a large silicon interposer, making it well suited to connecting high-capacity stacks with 12 layers or more. EMIB, by contrast, inserts small silicon bridges between chips, giving it advantages in modular designs and heterogeneous chip integration without requiring a large-area interposer.

South Korean Chipmakers Push to Eliminate HBM Back-End Bottlenecks

The same production pressures are affecting South Korea’s HBM supply chain. In the conventional DRAM market, supply was largely determined by the amount of wafer production capacity a manufacturer could secure. HBM, however, requires multiple DRAM dies to be vertically stacked before undergoing through-silicon via (TSV) processing, advanced packaging and final testing, meaning that any stage from front-end fabrication to back-end processing can become a production bottleneck. Moreover, as HBM and next-generation DRAM advance, process steps requiring extreme ultraviolet (EUV) lithography are accounting for a rapidly growing share of production. Access to advanced equipment has therefore emerged as another critical determinant of manufacturing capacity.

The volume of marketable HBM is effectively constrained by the lowest-throughput stage among the procurement of known-good dies for stacking, TSV interconnection, wafer thinning, bonding and molding, burn-in and final testing. If packaging-line expansion is delayed as DRAM wafer input increases, work in progress accumulates ahead of back-end processing, tying up a corresponding volume of HBM that would otherwise be delivered to customers.

SK hynix’s P&T7 advanced packaging fab under construction in Cheongju is a dedicated production base designed to address this bottleneck. SK hynix held a groundbreaking ceremony in April for P&T7 on a 231,000-square-meter site at Cheongju Technopolis and plans to invest a total of approximately $12.76 billion, with completion scheduled for 2028. Producing DRAM wafers for HBM at the adjacent M15X fab and conducting stacking, packaging and testing at P&T7 will shorten logistics routes between front-end and back-end processes while improving the synchronization of production planning.

Front-end investment is proceeding on the same timetable. SK hynix is investing approximately $13.43 billion in M15X to expand production capacity for next-generation DRAM, including HBM. It has also earmarked approximately $8.03 billion for a contract to introduce EUV lithography equipment from Dutch semiconductor equipment maker ASML by the end of 2027. The strategy of expanding wafer production capacity and packaging throughput in parallel reflects the manufacturing characteristics of HBM, whose supply depends on simultaneous capacity additions across both processes.

Samsung Electronics is likewise operating an integrated memory and packaging production system. The company began commercial shipments of sixth-generation HBM4 in February and started shipping samples of seventh-generation HBM4E in June. Cube-S, the 2.5-dimensional packaging platform developed by Samsung Foundry, is designed to place logic chips and HBM on a silicon interposer while controlling warpage in large-area packages. As Samsung Electronics expands capacity in anticipation of more than tripling its HBM revenue this year, it has incorporated the throughput of back-end operations responsible for memory stacking and logic integration into the same production expansion plan.

Packaging Race Fragments Across Process Niches as China Expands Infrastructure and Capacity in Tandem

As memory manufacturers extend their expansion plans into back-end processing, investment competition is also intensifying across individual segments of the packaging market. Separate markets are emerging for 2.5-dimensional packaging that combines logic chips with HBM, 3-dimensional packaging and hybrid bonding that vertically stack dies, silicon interposers and redistribution layers, organic package substrates, thermal-management materials and testing equipment. French market research firm Yole Group forecasts that the global advanced packaging market will grow from $46 billion in 2024 to more than $79.4 billion in 2030, representing a compound annual growth rate of 9.5%. The communications and infrastructure segment, where demand for AI accelerators, GPUs and chiplets is concentrated, is projected to record a compound annual growth rate of 14.9%.

The growing size of packages and number of wiring layers are also increasing the importance of substrates and materials. Japan’s Ibiden expects IC substrates for AI servers to expand from 80 millimeters by 80 millimeters in 2025 to at least 130 millimeters by 130 millimeters from 2030 onward. Ajinomoto of Japan estimates that it holds more than 95% of the global market for build-up film, or ABF, which is used as an interlayer insulating material in high-performance package substrates. SK hynix has also applied its advanced MR-MUF process to 12-high HBM4E, reducing thermal resistance by 17% compared with existing products. The physical properties of substrate insulators, encapsulants, underfill materials and thermally conductive adhesives suppress package warpage, cracking and heat generation, ultimately determining mass-production yields and long-term reliability.

Expanding order volumes for back-end processing companies are translating into large-scale capital investment. Taiwan’s ASE expects its leading-edge advanced packaging revenue to exceed $3.5 billion this year, representing growth of 10%, while US-based Amkor plans to invest as much as $7 billion in an advanced packaging and testing complex in Arizona. Initial production at the Amkor facility is scheduled for early 2028. Packaging plants must progress sequentially through equipment installation, process-condition establishment, reliability testing, customer qualification and yield stabilization, creating a substantial lag before announced investment plans translate into actual supply.

China is simultaneously expanding advanced packaging capacity and AI computing infrastructure. JCET, China’s largest OSAT provider, is investing approximately $1.15 billion to build an advanced packaging and testing facility in Shanghai’s Lingang district. Tongfu Microelectronics is also raising approximately $624 million to expand back-end capacity for memory, wafer-level packaging and high-performance computing.

These packaging investments are closely tied to the construction of computing infrastructure capable of absorbing domestically produced AI chips. Chinese government agencies are discussing plans to invest approximately $295.5 billion over the next five years to connect data centers nationwide and procure at least 80% of technologies, including AI chips, from domestic suppliers. Huawei has also unveiled the Atlas 950 SuperPoD, which connects 8,192 Ascend neural processing units. China intends to use these initiatives to establish an independent AI ecosystem spanning model development and service deployment. The strategy is aimed at linking AI chips, advanced packaging and computing infrastructure to create an environment in which semiconductors, software and application industries can grow together.