“No EUV? Use DUV”: China’s CXMT Advances Process Miniaturization as Domestic Semiconductor Ecosystem Expands Despite Lithography Gap

CXMT Establishes Fifth-Generation DRAM Process With DUV Multipatterning
DUV Deployment and EUV Development Accelerate Amid Disruptions to ASML Equipment Imports
Lithography Technology Gap Remains Wide, but Clear Growth Emerges Across Other Segments

Chinese DRAM manufacturer ChangXin Memory Technologies (CXMT) has begun mass-producing chips using a next-generation advanced process. With U.S.-led restrictions making access to extreme ultraviolet (EUV) lithography systems effectively impossible, the company is continuing to scale down its process nodes by combining deep ultraviolet (DUV) equipment with multipatterning technology. DUV-based multipatterning nevertheless faces clear limitations in process complexity, cost and yield, while efforts by Chinese companies to develop indigenous EUV systems have yet to produce meaningful results. Even so, market observers argue that these constraints are unlikely to impose a ceiling on the broader growth of China’s semiconductor industry, given the rapidly improving competitiveness of Chinese companies in other semiconductor equipment segments, including etching, deposition, cleaning and back-end processing.

CXMT Bets on DUV Processing

On the 20th, local time, CXMT announced at the 2026 World Manufacturing Convention in Hefei, Anhui Province, that it had developed and begun mass production of a fifth-generation DRAM process that reduces the spacing between critical DRAM memory-cell structures to 11.95 nanometers (nm, one billionth of a meter). The key to the process miniaturization was reportedly a multipatterning technique that uses DUV equipment to divide a circuit pattern into multiple exposures. CXMT said the process increases the number of chips produced from each wafer by at least 50% compared with the previous generation, adding that two 24-gigabit (Gb) low-power DRAM (LPDDR5X) products will be mass-produced using the process. An industry source said, “The 50% figure disclosed by CXMT refers to the total number of chips produced per wafer and should not be interpreted as a 50% improvement in actual yield.” The source added, however, that “if absolute DRAM production volumes increase, CXMT may gain additional supply capacity for products such as fourth-generation high-bandwidth memory (HBM3), where it has struggled to secure adequate yields.”

CXMT turned to DUV-based process miniaturization because U.S.-led export restrictions have constrained access to EUV lithography systems. U.S. restrictions on exports of lithography equipment to China began gathering momentum in 2018 and 2019 during President Donald Trump’s first administration. At the time, Washington pressured the Dutch government to block the renewal of export licenses that would have allowed ASML, the world’s sole supplier of EUV systems, to ship EUV lithography equipment to China. As a result, China has been unable to obtain EUV systems since 2019. In October 2022, the administration of President Joe Biden subsequently introduced sweeping export controls on advanced semiconductors and semiconductor manufacturing equipment, restricting both the supply of U.S.-made equipment and technology and production support by U.S. persons. Beginning in September 2023, the Netherlands also required government authorization for exports of ASML’s high-performance immersion DUV systems to China and other destinations. Lower-specification immersion DUV systems were brought under Dutch licensing requirements in September 2024, while the United States strengthened measures including its Foreign Direct Product (FDP) rule that December, extending the scope of its export controls to foreign-made semiconductor equipment incorporating U.S. technology or components.

Inherent Limitations of Multipatterning

Against this backdrop, CXMT and numerous other Chinese companies have adopted DUV-based multipatterning as an alternative route. In a conventional lithography process, a complete circuit pattern is contained on a single mask and transferred onto a wafer in one exposure. Multipatterning, by contrast, divides fine patterns that cannot be produced through a single exposure into two or more components, which are exposed and etched separately before being combined into a final circuit. Representative multipatterning techniques include litho-etch-litho-etch (LELE) and self-aligned double or quadruple patterning (SADP and SAQP). LELE exposes and etches an initial pattern before exposing and etching a second pattern between the first set of features. SADP and SAQP first create relatively widely spaced reference lines known as mandrels, then repeatedly deposit and etch thin spacer layers on both sides to double or quadruple line density.

The problem is that the limitations of multipatterning become increasingly pronounced as process geometries shrink. When multipatterning is used in advanced nodes, the exposure, deposition, etching and cleaning processes must be repeated several times to complete a single layer, substantially increasing both the number of process steps and overall production time. Because each pattern must also be aligned with nanometer-level precision, the risk of overlay errors rises. Minute variations in mandrel thickness or in spacer deposition and etching can accumulate, causing the final pattern to deviate from its intended position. These problems lead to lower yields and higher overall production costs.

Continued Push to Develop Indigenous EUV Systems

China’s semiconductor industry has also devoted substantial resources to developing indigenous EUV systems in an effort to overcome these constraints. The Changchun Institute of Optics, Fine Mechanics and Physics (CIOMP), an affiliate of the Chinese Academy of Sciences (CAS), began developing EUV lithography technology in 2008 under the “02 Project,” a major national science and technology initiative. In 2016, the institute announced that it had built a compact lithography optical system using a 13.5nm EUV light source and produced photoresist patterns with a linewidth of 32nm. The Institute of Optics and Electronics (IOE), another CAS affiliate participating in the same project, also secured technologies for vacuum systems, wafer and mask stages, vibration control and focus detection. These efforts constituted an early stage of research aimed at localizing the optical, precision-motion and vacuum systems required to develop commercial EUV equipment.

Efforts to secure the relevant technologies subsequently spread to the private sector. Shanghai Micro Electronics Equipment (SMEE), China’s largest lithography equipment manufacturer, filed a patent for an “EUV radiation generator and lithography equipment” in March 2023, which was published in September 2024. Huawei likewise filed patents covering mirrors and control technologies for EUV lithography systems in 2021 and an international patent for maskless EUV lithography technology using micromirrors in 2022. These filings have been interpreted as attempts to secure core technologies covering EUV light sources, reflective optics and patterning methods. China’s efforts have since progressed to the stage of integrated equipment. Reuters reported last December that “China completed a prototype of an indigenous EUV lithography system at a secure research facility in Shenzhen in January 2025 and began testing it.” According to multiple sources, the system was developed by former ASML engineers through the reverse engineering of ASML’s EUV platform and was built as a massive prototype occupying nearly an entire floor of the facility.

Table 1. China’s Efforts to Achieve Self-Sufficiency in Semiconductor Lithography Equipment

Replacing ASML Remains Difficult in the Near Term

China’s push for lithography self-sufficiency is also becoming more concrete in the DUV segment. According to reports published in July by Bloomberg, Reuters and other major international media outlets, Chinese state-owned company Shanghai Aishengna Electronic Technology Group has absorbed teams from domestic lithography startup Yuliangsheng and Shanghai Micro Electronics Equipment (SMEE) and is leading the production of DUV lithography systems. The companies aim to manufacture five systems this year and 20 next year, with future deliveries planned for leading Chinese semiconductor manufacturers including Semiconductor Manufacturing International Corp. (SMIC), Hua Hong Semiconductor and CXMT.

Experts remain divided in their assessments of China’s self-sufficiency strategy. Global investment bank JPMorgan has concluded that Chinese equipment still trails ASML’s products in resolution, throughput, system stability and yield, making it unlikely that the competitive landscape of the global lithography equipment market will change in the near term. Reuters similarly reported that Chinese systems lag behind ASML’s products in performance and reliability, limiting their immediate commercial threat. Semiconductor industry expert Paul Triolo, a partner at DGA-Albright Stonebridge Group, also told the South China Morning Post (SCMP), “Building equipment and delivering it to customers is entirely different from validating it for use in mass-production processes at a level that allows it to operate 24 hours a day throughout the year.”

A Way Forward for China’s Semiconductor Industry

Others argue that these challenges will not necessarily translate into a ceiling on the growth of China’s semiconductor industry. Chinese companies are steadily building competitiveness in areas beyond cutting-edge lithography systems. According to Georgetown University’s Center for Security and Emerging Technology (CSET), Chinese companies increased their global market share in etching and cleaning equipment for advanced packaging by approximately 10 percentage points between 2019 and 2024. In deposition equipment, China overtook Japan to become the world’s second-largest supplier after the United States. A leading company in this segment is NAURA Technology, China’s largest semiconductor equipment manufacturer. NAURA supplies equipment spanning the semiconductor manufacturing process, including etching, physical vapor deposition (PVD), chemical vapor deposition (CVD), cleaning, thermal processing, ion implantation and bonding.

Chinese companies have also established a pronounced presence in back-end processing. According to global market research firm TrendForce, JCET ranked third in the global outsourced semiconductor assembly and test (OSAT) market in 2024 with revenue of $5 billion. Tongfu Microelectronics ranked fourth with $3.32 billion, while Huatian Technology placed sixth with $2.01 billion. JCET is absorbing packaging demand for artificial intelligence (AI) PCs and smartphones, while Tongfu has secured U.S. fabless chipmaker AMD as a major customer and is expanding its communications and computing semiconductor packaging operations. A similar trend is visible in the testing equipment market. CSET data show that Chinese companies’ global share of linear and discrete semiconductor testing equipment has risen to approximately 70% since 2019. Companies leading this growth include Hangzhou-based Changchuan Technology and Beijing-based AccoTEST.